Loop gain analysis
PCB - top view
THD - plots
Capactive load test
This is my first IPS board I have made with SMD components. I was suprised that it is way easier to solder it than the boards with THT components.
The topology is very simple, two symetric LTP's and CFP cascoded VAS stage as in MK1 version. The only trick is that the unsymmetrical current mirrors are now part of the VAS stage so the problem with ''undetermined'' bias is gone (it is now determined by current mirror ratio and LTP bias value).
Compensation provides ULGF point at about 320kHz, PM=60deg and GM=25dB which is nice and safe.