• GrandMOS - schematic

    GrandMOS - schematic

  • PCB


  • Loop gain anaysis

    Loop gain anaysis

Just for educational purposes I have made copy of GrandMOS project. Project is made as close as possible to the original version but the latfet VAS transistors are substituted with IRF610 and IRF9610. To keep about the same OLG I had to add two LED diodes for equalizing Vgs voltages in between 2SJ/2SK and IRF transistors. IRF drivers are placed on the small heatsink, VAS stage bias is thermally stabilized by NPN transistor (a bit over compensated for safety reasons). The amplifier is running without compensation but for safety reasons it is better to solder it anyway (loop gain analysis bellow).

Is it done right way ? That is questionable, IRF transistors are highly non linear in VAS stage, quite high output impedance of voltage stage doesn't provide good/proper drive for the output devices.

Does it always have to be right ? Does THD and other performance factors have to be at top notch ? In my opinion not really, the right way to go is the way we like :D

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